1. Field of the Invention
The present invention relates to an input buffer circuit for use as a first-stage input circuit of a semiconductor integrated circuit device comprising a digital logic circuit or an interface between digital logic circuits.
2. Description of the Related Art
Input buffer circuits of the type described above are required to be of a high input impedance and a low output impedance, and also to be capable of outputting an input logic level at an accurate and stable level. It is also necessary for such input buffer circuits to keep a suitable noise margin so that they will not reverse the logic level in error due to noise in a power supply line.
Such a logic level reversal is caused for the following reasons:
A constant-voltage power supply line for supplying a constant bias voltage to an input buffer circuit is not dedicated to the input buffer circuit, but is shared by other logic circuits. The constant bias voltage is supplied from the constant-voltage power supply line through metallic layers, leads, and interconnections on a semiconductor substrate. Those metallic layers, leads, and interconnections have their equivalent resistance, equivalent inductance, etc., which cannot be removed. Therefore, even though a constant-voltage power supply produces an ideally constant voltage at its output terminal, the voltage on the power supply line tends to be varied by a relatively large consumed current when the logic circuits reverse the logic level, i.e., when the logic level undergoes a transition. The variation in the voltage causes the logic circuits to affect each other through current lines, resulting in an erroneous logic level reversal in a certain logic circuit. Particularly, those logic circuits which are involved in outputting data consume a relatively large current upon a logic level transition, and they bring about a logic level transition substantially simultaneously. Therefore, the voltage on the power supply line suffers a very large variation, which causes a power supply voltage lower than an inputted logic level to be instantaneously applied to an input buffer circuit in a certain location that in turn develops an erroneous logic level reversal.
Such an erroneous logic level reversal also often happens when a logic level is inputted to an input buffer circuit and thereafter a logic circuit of a stage next to the input buffer circuit undergoes a logic level transition, which produces a large change in the voltage on the power supply line that is fed back to the input buffer circuit.
For providing a noise margin to prevent the erroneous logic level reversal, it is necessary to give the input buffer circuit appropriate hysteresis characteristics as known in the art.
Hereinafter, a logic level reversal operation of an input buffer circuit will be referred to as a "first transition", and a substantially simultaneous logic reversal operation of other logic circuits than the input buffer circuits, e.g., logic circuits for outputting data or logic circuits at a stage next to the input buffer circuit, will be referred to as a "second transition".
The input buffer circuit requires no hysteresis characteristics as mentioned above in order to accurately capture an input logic level at the time of the first transition. However, the input buffer circuit should be provided with a comparatively large hysteresis interval, i.e., a shift quantity, in order to prevent itself from suffering an erroneous logic level reversal at the time of the second transition.
One conventional input buffer circuit as disclosed in Japanese laid-open patent publication No. 4-100411 will be described below with reference to FIG. 1 of the accompanying drawings.
As shown in FIG. 1, an input buffer circuit comprises a CMOS (complementary metal-oxide-semiconductor) inverter comprising a P-channel FET (field-effect transistor) P1 and an N-channel FET N1, an array of P-channel FETs P3, P2 and N-channel FETs N2, N3 connected in series between a power supply terminal 71 and a ground terminal 72, for receiving an output signal from the CMOS inverter, an inverter 73 for receiving a signal from a junction between the FETs P1, N1 and a junction between the FETs P2, N2 and outputting an inverted signal as an output signal Ao to an output terminal 75, a delay circuit 76 for receiving and delaying a signal from the output terminal 75, and a low-transition detecting circuit 77 and a high-transition detecting circuit 78 for receiving an output signal from the delay circuit 76 and outputting respective signals to the respective gates of the FETs P3, N3.
An input terminal 74 is connected to the gates of the FETs P1, P2, N1, N2. The FETs P1, N1 have respective power supply terminals connected commonly to the power supply terminal 71 and the ground terminal 72 of the FETs P3, P2, N2, N3.
FIG. 2 of the accompanying drawings shows a timing chart illustrative of operation of the input buffer circuit shown in FIG. 1. If an input signal Ai supplied from the input terminal 74 comprises a negative pulse, then an output waveform from the delay circuit 76 is outputted with a time delay of td2 from the input signal Ai. The low-transition detecting circuit 77 outputs a low level for a certain period of time from a time T2 immediately after the output waveform from the delay circuit 76 shifts from a high level to a low level to a time T3. In response to the low level outputted from the low-transition detecting circuit 77, the FET P3 is rendered conductive. Since the FETs P1, P2 are conductive and the FET N3 is nonconductive, a logic threshold VthH for the input signal Ai is high, increasing a margin for keeping the low level of the input buffer circuit.
For a period of time from a time T4 to a time T5, during which an output signal from the high-transition detecting circuit 78 is of a high level due to an output signal from the delay circuit 76, the FETs N3, N1, N2 are rendered conductive and the FET P3 is rendered nonconductive, lowering a logic threshold VthL for the input signal Ai. Therefore, the input buffer circuit has a large margin for keeping the high level.
FIG. 3 of the accompanying drawings shows the relationship between the logic threshold VthL and the logic threshold VthH. In FIG. 3, the horizontal axis represents the voltage (V) of the input signal Ai, and the vertical axis represents the input voltage (V) applied to the inverter 73, i.e., an inverted value of the output signal Ao. A threshold VthM intermediate between the low and high thresholds VthL, VthH prevails when both the FETs P3, N3 are nonconductive over a period of time between the times T3, T4 shown in FIG. 2.
The periods of time between the times T2, T3 and between the times T4, T5 are a transition period for outputting data from the logic system of the input buffer circuit, i.e., a second transition period. The delay time of the delay circuit 76 is adjusted to cover the second transition period.
The above publication does not disclose any circuit arrangement of the low-transition detecting circuit 77 and the high-transition detecting circuit 78. One example of these circuits 77, 78 will be described below with reference to FIGS. 4(A) and 4(B) of the accompanying drawings.
As shown in FIG. 4(A), the low-transition detecting circuit comprises a NOR gate for being supplied with an input signal and a signal produced by processing the input signal with an opposite-phase delay element, and an inverter for being supplied with an output signal from the NOR gate. The low-transition detecting circuit of this arrangement outputs a logic level 0 only when two input signals applied to the NOR gate are of a level 0.
As shown in FIG. 4(B), the high-transition detecting circuit is similar to the low-transition detecting circuit shown in FIG. 4(A) except that a NAND gate is connected in place of the NOR gate shown in FIG. 4(A). The high-transition detecting circuit of this arrangement outputs a logic level 1 only when two input signals applied to the NAND gate are of a level 1.
The opposite-phase delay element shifts the input signal into opposite phase, i.e., produces an inverted value of the input signal, and delays the same.
With the conventional input buffer circuit shown in FIG. 1, the delay time td2 of the delay circuit 76 is adjusted to shift the logic thresholds into alignment with the second transition period for thereby preventing the input buffer circuit from operating in error upon a data output transition when power supply noise is most likely to occur.
Input signals applied to the input buffer circuit are not limited to the input signal Ai shown in FIG. 2. The input buffer circuit may be supplied with an input waveform in which a dummy cycle is present as shown in FIG. 5 of the accompanying drawings. The dummy cycle is a period of time in which only addresses are idly cycled in a standby condition of a system which uses integrated circuits (ICs).
In FIG. 5 when the low-transition detecting circuit 77 generates a low-level pulse between times T6 and T8 in a certain period of time from a time TE at which a final dummy waveform is inputted, the logic threshold VthH is high during the period of the low-level pulse. If the input signal Ai changes from the low level to the high level during this time, the time to output high level data is delayed, and hence the outputting of the data cannot be speeded up due to the delay. In some cases, the high level data cannot be outputted.
If a logic circuit is used as a static operation system, then even when an input signal applied to an input buffer circuit undergoes several transitions, a delay time from the final transition to the outputting of final data has to fall within a predetermined range, also posing the problem of a speed delay.
Moreover, a transition of the output of data may not necessarily occur after elapse of the time td2 from the input signal Ai, but may occur with slight variations of time. Consequently, no accurate time matching can be achieved if the time td2 is determined on the basis of the output signal Ao. Rather, it has been found out that it is more accurate to directly detect and use the time of a transition of an output driver or the like.
The conventional input buffer circuit is further problematic in that inasmuch the above transition detecting circuits need to be added to all input buffer circuits, but no common transition detecting circuits are available which would otherwise be shared by all input buffer circuits, the number of constituent elements increases, imposing a limitation on efforts to reduce the chip size.